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RTAS
1997
IEEE
13 years 12 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
14 years 19 days ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
DAC
2004
ACM
14 years 8 months ago
Circuit-aware architectural simulation
Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. However, ...
Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Tod...
ASIAMS
2008
IEEE
14 years 2 months ago
High-Performance Carry Select Adder Using Fast All-One Finding Logic
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but w...
Sun Yan, Zhang Xin, Jin Xi
ASPDAC
2008
ACM
151views Hardware» more  ASPDAC 2008»
13 years 9 months ago
High performance current-mode differential logic
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Ch...