1224 search results - page 107 / 245 » Design and Implementation of a Practical Parallel Delaunay A... |
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ICDCS
2009
IEEE
16 years 1 months ago
2009
IEEE
Autonomous routing algorithms, such as BGP, are intended to reach a globally consistent set of routes after nodes iteratively and independently collect, process, and share network...
131
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ARC
2008
Springer
15 years 6 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
153
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HOTI
2002
IEEE
15 years 9 months ago
2002
IEEE
High-performance input-queued switches require highspeed scheduling algorithms while maintaining good performance. Various round-robin scheduling algorithms for Virtual Output Que...
124
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FPL
2001
Springer
15 years 9 months ago
2001
Springer
This paper presents an FPGA-based implementation of a syntactic parser that can process languages generated by almost unrestricted real-life context-free grammars (CFGs). More prec...
129
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CONCUR
1991
Springer
15 years 8 months ago
1991
Springer
This paper deals with verification methods based on equivalence relations between labeled transition systems. More precisely, we are concerned by two practical needs: how to effi...