164 search results - page 3 / 33 » Design and Implementation of the Memory Scheduler for the PC... |
TON
2008
13 years 8 months ago
2008
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
The primary goal of the Multimedia Router (MMR) project is the design and implementation of a router optimized for multimedia applications. The router is targeted for use in clust...
ANCS
2009
ACM
13 years 6 months ago
2009
ACM
As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing e...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...