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» Design and Implementation of the NUMAchine Multiprocessor
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TVLSI
2010
13 years 3 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
SIGARCH
2008
107views more  SIGARCH 2008»
13 years 8 months ago
Multitasking workload scheduling on flexible core chip multiprocessors
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
Divya Gulati, Changkyu Kim, Simha Sethumadhavan, S...
JSA
2010
173views more  JSA 2010»
13 years 3 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
ASPLOS
1994
ACM
14 years 16 days ago
Reactive Synchronization Algorithms for Multiprocessors
Synchronization algorithms that are efficient across a wide range of applications and operating conditions are hard to design because their performance depends on unpredictable ru...
Beng-Hong Lim, Anant Agarwal
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 2 months ago
Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications
This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0...
Tero Arpinen, Petri Kukkala, Erno Salminen, Marko ...