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DAC
2005
ACM
13 years 10 months ago
Performance space modeling for hierarchical synthesis of analog integrated circuits
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
Georges G. E. Gielen, Trent McConaghy, Tom Eeckela...
DAWAK
2006
Springer
13 years 11 months ago
Extending Visual OLAP for Handling Irregular Dimensional Hierarchies
Comprehensive data analysis has become indispensable in a variety of environments. Standard OLAP (On-Line Analytical Processing) systems, designed for satisfying the reporting need...
Svetlana Mansmann, Marc H. Scholl
FM
2008
Springer
127views Formal Methods» more  FM 2008»
13 years 9 months ago
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
TLM (Transaction-Level Modeling) was introduced to cope with the increasing complexity of Systems-on-Chip designs by raising the modeling level. Currently, TLM is primarily used fo...
Olivier Ponsini, Wendelin Serwe
DATE
2002
IEEE
73views Hardware» more  DATE 2002»
14 years 26 days ago
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley...
DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
14 years 2 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards