529 search results - page 62 / 106 » Design and Test Space Exploration of Transport-Triggered Arc... |
DSD
2004
IEEE
14 years 18 days ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
CHES
2007
Springer
14 years 3 months ago
2007
Springer
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
SAMOS
2005
Springer
14 years 2 months ago
2005
Springer
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
IJHPCA
2010
13 years 7 months ago
2010
As high-end computing systems continue to grow in scale, recent advances in multiand many-core architectures have pushed such growth toward more denser architectures, that is, mor...