254 search results - page 13 / 51 » Design and VLSI Implementation of a Unified Synapse-Neuron A... |
DFT
1999
IEEE
13 years 11 months ago
1999
IEEE
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
VLSI
2007
Springer
14 years 1 months ago
2007
Springer
Abstract— In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking ...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
ARVLSI
1999
IEEE
13 years 11 months ago
1999
IEEE
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
FCCM
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper proposes a high performance least square solver on FPGAs using the Cholesky decomposition method. Our design can be realized by iteratively adopting a single triangular...