254 search results - page 4 / 51 » Design and VLSI Implementation of a Unified Synapse-Neuron A... |
ISCAS
2003
IEEE
14 years 20 days ago
2003
IEEE
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
ISCAS
2003
IEEE
14 years 20 days ago
2003
IEEE
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...