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CODES
2001
IEEE
13 years 10 months ago
Hardware/software partitioning of embedded system in OCAPI-xl
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...
Geert Vanmeerbeeck, Patrick Schaumont, Serge Verna...
EGH
2004
Springer
14 years 4 days ago
Realtime ray tracing of dynamic scenes on an FPGA chip
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
Jörg Schmittler, Sven Woop, Daniel Wagner, Wo...
PLDI
2011
ACM
12 years 9 months ago
Caisson: a hardware description language for secure information flow
Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s roo...
Xun Li 0001, Mohit Tiwari, Jason Oberg, Vineeth Ka...
ERSA
2004
129views Hardware» more  ERSA 2004»
13 years 8 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
12 years 10 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...