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» Design and evaluation of an auto-memoization processor
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JSS
2006
104views more  JSS 2006»
13 years 7 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
INTEGRATION
2007
98views more  INTEGRATION 2007»
13 years 7 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
DSD
2009
IEEE
88views Hardware» more  DSD 2009»
13 years 5 months ago
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
RTAS
2005
IEEE
14 years 1 months ago
VPN Gateways over Network Processors: Implementation and Evaluation
Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, ...
Yi-Neng Lin, Chiuan-Hung Lin, Ying-Dar Lin, Yuan-C...
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Power estimation starategies for a low-power security processor
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling C...