620 search results - page 4 / 124 » Design and evaluation of an auto-memoization processor |
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
EUROPAR
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
APCSAC
2001
IEEE
13 years 11 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
MICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
JILP
2002
13 years 7 months ago
2002
As microprocessor designs continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models...