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» Design and evaluation of an auto-memoization processor
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IPPS
2005
IEEE
15 years 10 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
CF
2004
ACM
15 years 8 months ago
Reducing traffic generated by conflict misses in caches
Off-chip memory accesses are a major source of power consumption in embedded processors. In order to reduce the amount of traffic between the processor and the off-chip memory as ...
Pepijn J. de Langen, Ben H. H. Juurlink
DTJ
1998
171views more  DTJ 1998»
15 years 4 months ago
Measurement and Analysis of C and C++ Performance
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
Hemant G. Rotithor, Kevin W. Harris, Mark W. Davis
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
13 years 11 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
ICCAD
1995
IEEE
97views Hardware» more  ICCAD 1995»
15 years 7 months ago
Interface co-synthesis techniques for embedded systems
A key aspect of the synthesis of embedded systems is the automatic integration of system components. This entails the derivation of both the hardware and software interfaces that ...
Pai H. Chou, Ross B. Ortega, Gaetano Borriello