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» Design and evaluation of an auto-memoization processor
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CDES
2008
166views Hardware» more  CDES 2008»
15 years 5 months ago
Scalable Directory Organization for Tiled CMP Architectures
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
Alberto Ros, Manuel E. Acacio, José M. Garc...
TVLSI
2002
121views more  TVLSI 2002»
15 years 4 months ago
On-chip decoupling capacitor optimization using architectural level prediction
Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills
SEUS
2010
IEEE
15 years 2 months ago
Code Generation for Embedded Java with Ptolemy
Abstract. Code generation from models is the ultimate goal of model-based design. For real-time systems the generated code must be analyzable for the worstcase execution time (WCET...
Martin Schoeberl, Christopher Brooks, Edward A. Le...
ASPLOS
2004
ACM
15 years 9 months ago
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
IPPS
2007
IEEE
15 years 10 months ago
Design Alternatives for a High-Performance Self-Securing Ethernet Network Interface
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
Derek L. Schuff, Vijay S. Pai