620 search results - page 86 / 124 » Design and evaluation of an auto-memoization processor |
178
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FPGA
2010
ACM
15 years 4 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
172
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ISCA
2012
IEEE
13 years 6 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
143
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DOCENG
2003
ACM
15 years 9 months ago
2003
ACM
We introduce a lazy XSLT interpreter that provides random access to the transformation result. This allows efficient pipelining of transformation sequences. Nodes of the result tr...
126
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DAC
2004
ACM
16 years 5 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
142
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RTCSA
2007
IEEE
15 years 10 months ago
2007
IEEE
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...