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» Design and implementation of WIRE Diameter
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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 2 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
DAC
2002
ACM
14 years 10 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
14 years 4 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
PATMOS
2005
Springer
14 years 3 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
ICC
2007
IEEE
133views Communications» more  ICC 2007»
14 years 4 months ago
An Energy-Aware Multi-Hop Tree Scatternet for Bluetooth Networks
Abstract— Bluetooth is an enabling technology used to construct personal area networks. Since Bluetooth devices are usually energy-constrained, a critical issue for Bluetooth net...
Yuanyuan Zhou, Muralidhar Medidi