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» Design and implementation of WIRE Diameter
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ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 9 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
JSAC
2010
142views more  JSAC 2010»
13 years 4 months ago
Handling inelastic traffic in wireless sensor networks
The capabilities of sensor networking devices are increasing at a rapid pace. It is therefore not impractical to assume that future sensing operations will involve real time (inela...
Jiong Jin, Avinash Sridharan, Bhaskar Krishnamacha...
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
14 years 4 months ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
HPCA
2008
IEEE
14 years 10 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
ICFP
2008
ACM
14 years 9 months ago
Functional netlists
In efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description la...
Sungwoo Park, Jinha Kim, Hyeonseung Im