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FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
15 years 10 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
USENIX
2007
15 years 7 months ago
Load Shedding in Network Monitoring Applications
Monitoring and mining real-time network data streams is crucial for managing and operating data networks. The information that network operators desire to extract from the network...
Pere Barlet-Ros, Gianluca Iannaccone, Josep Sanju&...
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
146
Voted
CIDR
2009
167views Algorithms» more  CIDR 2009»
15 years 5 months ago
Unbundling Transaction Services in the Cloud
The traditional architecture for a DBMS engine has the recovery, concurrency control and access method code tightly bound together in a storage engine for records. We propose a di...
David B. Lomet, Alan Fekete, Gerhard Weikum, Micha...
130
Voted
DAC
2002
ACM
16 years 5 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...