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GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
DASIP
2010
14 years 11 months ago
Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation
This paper proposes an automatic design flow from userfriendly design to efficient implementation of video processing systems. This design flow starts with the use of coarsegrain ...
Ruirui Gu, Jonathan Piat, Mickaël Raulet, J&o...
CCECE
2009
IEEE
15 years 11 months ago
An ultra compact block cipher for serialized architecture implementations
In this paper, we present a new block cipher, referred as PUFFIN2, that is designed to be used with applications requiring very low circuit area. PUFFIN2 is designed to be impleme...
Cheng Wang, Howard M. Heys
FPL
2006
Springer
147views Hardware» more  FPL 2006»
15 years 8 months ago
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
DELTA
2006
IEEE
15 years 8 months ago
Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmabl
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
Peter J. Green, Desmond P. Taylor