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» Design and implementation of correlating caches
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ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
14 years 11 days ago
Using a User-Level Memory Thread for Correlation Prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
Yan Solihin, Josep Torrellas, Jaejin Lee
HPCA
1996
IEEE
13 years 11 months ago
Predictive Sequential Associative Cache
In this paper, we propose a cache design that provides the same miss rate as a two-way set associative cache, but with a access time closer to a direct-mapped cache. As with other...
Brad Calder, Dirk Grunwald, Joel S. Emer
MICRO
1997
IEEE
110views Hardware» more  MICRO 1997»
13 years 11 months ago
The Design and Performance of a Conflict-Avoiding Cache
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
Nigel P. Topham, Antonio González, Jos&eacu...
ADHOC
2007
135views more  ADHOC 2007»
13 years 7 months ago
Mitigating the gateway bottleneck via transparent cooperative caching in wireless mesh networks
Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congest...
Saumitra M. Das, Himabindu Pucha, Y. Charlie Hu
PPOPP
2010
ACM
14 years 4 months ago
The LOFAR correlator: implementation and performance analysis
LOFAR is the first of a new generation of radio telescopes. Rather than using expensive dishes, it forms a distributed sensor network that combines the signals from many thousands...
John W. Romein, P. Chris Broekema, Jan David Mol, ...