584 search results - page 9 / 117 » Design and implementation of correlating caches |
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Caches often employ write-back instead of writethrough, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however...
ICPP
2009
IEEE
13 years 5 months ago
2009
IEEE
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
CANPC
1999
Springer
13 years 11 months ago
1999
Springer
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...