67 search results - page 6 / 14 » Design and verification of long-running transactions in a ti... |
FDL
2003
IEEE
14 years 23 days ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
ACSD
2006
IEEE
13 years 9 months ago
2006
IEEE
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
TCAD
2008
13 years 7 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. Such algorithms can be at times ineffective ...
DSN
2004
IEEE
13 years 11 months ago
2004
IEEE
It is often the case that safety-critical systems have to be reconfigured during operation because of issues such as changes in the system's operating environment or the fail...