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ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 6 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
FPGA
2009
ACM
183views FPGA» more  FPGA 2009»
14 years 4 months ago
HW/SW methodologies for synchronization in FPGA multiprocessors
Modern Field Programmable Gate Arrays (FPGA) can be programmed with multiple soft-core processors. These solutions can be used for MultiProcessor Systems-on-Chip (MPSoCs) prototyp...
Antonino Tumeo, Christian Pilato, Gianluca Palermo...
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 4 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
CONTEXT
2007
Springer
14 years 4 months ago
Between Symbol and Language-in-use
Indexing is often designed with the intent of dimensional reduction, that is, of generating standardised and uniform descriptive metadata. This could be characterised as a process ...
Emma Tonkin
ICPPW
2006
IEEE
14 years 4 months ago
Model Checking Control Communication of a FACTS Device
This paper concerns the design and verification of a realtime communication protocol for sensor data collection and processing between an embedded computer and a DSP. In such sys...
David A. Cape, Bruce M. McMillin, James K. Townsen...