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» Design diagnosis using Boolean satisfiability
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DATE
2009
IEEE
100views Hardware» more  DATE 2009»
14 years 5 months ago
Increasing the accuracy of SAT-based debugging
Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. I...
André Sülflow, Görschwin Fey, C&e...
ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
13 years 11 months ago
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both...
Weixun Wang, Xiaoke Qin, Prabhat Mishra
DAC
2005
ACM
14 years 11 months ago
Structural search for RTL with predicate learning
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting...
ICCAD
2002
IEEE
227views Hardware» more  ICCAD 2002»
14 years 7 months ago
Generic ILP versus specialized 0-1 ILP: an update
Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
ICNP
2007
IEEE
14 years 5 months ago
Network Court Protocol and Malicious Node Conviction
- A Network Court Protocol is designed for malicious node conviction based on information from network node accusing and testifying operations, which are formally modeled by algebr...
Na Li, David Lee