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ICCD
2004
IEEE
126views Hardware» more  ICCD 2004»
16 years 1 months ago
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
Joshua L. Kihm, Daniel A. Connors
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
16 years 1 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ICCAD
2005
IEEE
151views Hardware» more  ICCAD 2005»
16 years 1 months ago
Architecture and details of a high quality, large-scale analytical placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Andrew B. Kahng, Sherief Reda, Qinke Wang
CVPR
2010
IEEE
16 years 14 days ago
Learning Mid-Level Features For Recognition
Many successful models for scene or object recognition transform low-level descriptors (such as Gabor filter responses, or SIFT descriptors) into richer representations of interme...
Y-Lan Boureau, Francis Bach, Yann LeCun, Jean Ponc...
VEE
2010
ACM
247views Virtualization» more  VEE 2010»
15 years 11 months ago
Capability wrangling made easy: debugging on a microkernel with valgrind
Not all operating systems are created equal. Contrasting traditional monolithic kernels, there is a class of systems called microkernels more prevalent in embedded systems like ce...
Aaron Pohle, Björn Döbel, Michael Roitzs...
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