59 search results - page 4 / 12 » Design for Verification in System-level Models and RTL |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
CL
2010
Springer
13 years 7 months ago
2010
Springer
In this paper we present the syntax, semantics, and compilation of a new system-level programming language called SystemJ. SystemJ is a multiclock language supporting the Globally...
FDL
2008
IEEE
13 years 9 months ago
2008
IEEE
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...