59 search results - page 5 / 12 » Design for Verification in System-level Models and RTL |
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
EUROMICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...