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FMCAD
2004
Springer
14 years 2 months ago
Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs
Late changes in silicon design (ECO) is a common although undesired practice. The need for ECO exists even in high-level design flows since bugs may occur in the specifications, ...
Laurent Arditi, Gérard Berry, Michael Kishi...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 6 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
TWC
2008
137views more  TWC 2008»
13 years 9 months ago
Decoding, Performance Analysis, and Optimal Signal Designs for Coordinate Interleaved Orthogonal Designs
Space-time block codes (STBC) using coordinate interleaved orthogonal designs (CIOD) proposed recently by Khan and Rajan allow single-complex symbol decoding and offer higher data ...
Dung Ngoc Dao, Chintha Tellambura
GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
ASPDAC
2008
ACM
72views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Design rule optimization of regular layout for leakage reduction in nanoscale design
Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wan...