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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
ICCAD
2004
IEEE
80views Hardware» more  ICCAD 2004»
14 years 6 months ago
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the res...
Jintae Kim, Jaeseo Lee, Lieven Vandenberghe
DSD
2011
IEEE
194views Hardware» more  DSD 2011»
12 years 9 months ago
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
VTS
2002
IEEE
128views Hardware» more  VTS 2002»
14 years 2 months ago
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models
A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulations experiments are design...
Abhishek Singh, Jim Plusquellic, Anne E. Gattiker
CONEXT
2007
ACM
14 years 1 months ago
A cross-layer load-independent link cost metric for wireless mesh networks
We present Cross-layer Unicast Transmission Time (X-UTT), a MAC-aware load-independent link cost metric for 802.11based wireless mesh networks. X-UTT utilizes information acquired...
Marianna Carrera, Henrik Lundgren, Theodoros Salon...