231 search results - page 15 / 47 » Design issues for dynamic voltage scaling |
JCSC
2002
13 years 7 months ago
2002
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
CASES
2005
ACM
13 years 9 months ago
2005
ACM
Dynamic frequency scaling and dynamic voltage scaling have been developed to save power and/or energy for general purpose computing platforms and high-end embedded systems. This p...
SIGMETRICS
2010
ACM
14 years 6 days ago
2010
ACM
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based o...
CODES
2007
IEEE
13 years 9 months ago
2007
IEEE
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
ICS
2004
Tsinghua U.
14 years 22 days ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...