125 search results - page 14 / 25 » Design of Asynchronous Circuits Using Synchronous CAD Tools |
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
CHES
2004
Springer
14 years 2 months ago
2004
Springer
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...
CAD
2002
Springer
13 years 8 months ago
2002
Springer
Deformation of 3D shapes usually requires the use of a deformation tool. The freeform deformation technique requires the use of a lattice of control point for deforming an object....
TVLSI
2010
13 years 3 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
ERSA
2010
13 years 6 months ago
2010
In this paper, we introduce the open-source PivPav backend tool for reconfigurable computing. Essentially, PivPav provides an interface to a library of digital circuits that are ke...