82 search results - page 5 / 17 » Design of Asynchronous Controllers with Delay Insensitive In... |
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
ISMVL
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
ASYNC
1998
IEEE
13 years 11 months ago
1998
IEEE
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays inc...
DELTA
2006
IEEE
13 years 11 months ago
2006
IEEE
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
VLSI
2010
Springer
13 years 5 months ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...