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131
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DAC
2002
ACM
16 years 3 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
WSC
2007
15 years 4 months ago
Hierarchical planning and multi-level scheduling for simulation-based probabilistic risk assessment
Simulation of dynamic complex systems—specifically, those comprised of large numbers of components with stochastic behaviors—for the purpose of probabilistic risk assessment f...
Hamed Nejad, Dongfeng Zhu, Ali Mosleh
114
Voted
CF
2007
ACM
15 years 6 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
119
Voted
CF
2006
ACM
15 years 6 months ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
SIGCOMM
1998
ACM
15 years 6 months ago
Quality of Service Based Routing: A Performance Perspective
Recent studies provide evidence that Quality ofService QoS routing can provide increased network utilization compared to routing that is not sensitive to QoS requirements of tra...
George Apostolopoulos, Roch Guérin, Sanjay ...