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APCSAC
2001
IEEE
13 years 11 months ago
Retargetable Cache Simulation Using High Level Processor Models
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
Rajiv A. Ravindran, Rajat Moona
SPRINGSIM
2010
13 years 6 months ago
SES-based ontological process for high level information fusion
—Data Fusion (DF) process is in the interest of the military community since it provides the opportunity to achieve information superiority. The System Entity Structure (SES) is ...
Hojun Lee, Bernard P. Zeigler
TVLSI
2008
120views more  TVLSI 2008»
13 years 7 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
IESS
2007
Springer
128views Hardware» more  IESS 2007»
14 years 1 months ago
An Interactive Design Environment for C-based High-Level Synthesis
: Much effort in RTL design has been devoted to developing “push-button” types of tools. However, given the highly complex nature, and lack of control on RTL design, push-butt...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
EURODAC
1995
IEEE
135views VHDL» more  EURODAC 1995»
13 years 11 months ago
A high performance VHDL simulator for large systems design
The requirements of large system design place great demands upon the performance and diagnostic capabilities of simulation. This paper explains how these requirements have been sa...
Steve Hodgson, Zak Shaar, Andy Smith