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» Design of Neuromorphic Hardwares
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PLDI
2011
ACM
13 years 1 months ago
Understanding POWER multiprocessors
Exploiting today’s multiprocessors requires highperformance and correct concurrent systems code (optimising compilers, language runtimes, OS kernels, etc.), which in turn requir...
Susmit Sarkar, Peter Sewell, Jade Alglave, Luc Mar...
INFOCOM
2009
IEEE
14 years 5 months ago
An Experimental Evaluation of Rate Adaptation for Multi-Antenna Systems
—Increasingly wireless networks use multi-antenna nodes as in IEEE 802.11n and 802.16. The Physical layer (PHY) in such systems may use the antennas to provide multiple streams o...
Wonsoo Kim, O. Khan, Kien T. Truong, Soon-Hyeok Ch...
IWOMP
2007
Springer
14 years 5 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...
SPAA
2006
ACM
14 years 4 months ago
Astronomical real-time streaming signal processing on a Blue Gene/L supercomputer
LOFAR is the first of a new generation of radio telescopes, that combines the signals from many thousands of simple, fixed antennas, rather than from expensive dishes. Its revol...
John W. Romein, P. Chris Broekema, Ellen van Meije...
SPAA
2004
ACM
14 years 4 months ago
Cache-oblivious shortest paths in graphs using buffer heap
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
Rezaul Alam Chowdhury, Vijaya Ramachandran
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