62 search results - page 7 / 13 » Design of a Predictive Filter Cache for Energy Savings in Hi... |
CF
2005
ACM
13 years 9 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
ISLPED
2003
ACM
14 years 24 days ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...