Sciweavers

253 search results - page 19 / 51
» Design of a logic element for implementing an asynchronous F...
Sort
View
FPL
2000
Springer
130views Hardware» more  FPL 2000»
13 years 11 months ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...
ICISC
2009
125views Cryptology» more  ICISC 2009»
13 years 5 months ago
Power Analysis of Single-Rail Storage Elements as Used in MDPL
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
Amir Moradi, Thomas Eisenbarth, Axel Poschmann, Ch...
FPL
2005
Springer
114views Hardware» more  FPL 2005»
14 years 1 months ago
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Buildi
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
Andy Gean Ye, Jonathan Rose
ASPDAC
2007
ACM
80views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic
Abstract-- A complementary ferroelectriccapacitor (CFC) logic-circuit style is proposed for a compact and standby-power-free content-addressable memory (CAM). Since the use of the ...
Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura,...
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 1 months ago
HIBI-based multiprocessor SoC on FPGA
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
Erno Salminen, Ari Kulmala, Timo D. Hämä...