220 search results - page 29 / 44 » Design of an Optimal Test Access Architecture Using a Geneti... |
FPL
2009
Springer
14 years 8 days ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
IPSN
2007
Springer
14 years 1 months ago
2007
Springer
We present the design and implementation of the Illuminator, a preliminary sensor network-based intelligent light control system for entertainment and media production. Unlike mos...
GECCO
2006
Springer
13 years 11 months ago
2006
Springer
This paper presents a new method for 3D cutting of geometrical space with application to airspace sectoring. This problem comes from the air traffic management but the proposed me...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...