195 search results - page 30 / 39 » Design of clocked circuits using UML |
FPL
2006
Springer
14 years 21 days ago
2006
Springer
Given large circuit sizes, high clock frequencies, and possibly extreme operating environments, Field Programmable Gate Arrays (FPGAs) are capable of heating beyond their designed...
QEST
2010
IEEE
13 years 7 months ago
2010
IEEE
Traditional architecture design approaches hide hardware uncertainties from the software stack through overdesign, which is often expensive in terms of power consumption. The recen...
TVLSI
1998
13 years 8 months ago
1998
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
Abstract- This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown t...