195 search results - page 5 / 39 » Design of clocked circuits using UML |
ICCAD
1997
IEEE
14 years 16 hour ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
TCAD
2002
13 years 7 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
DATE
2000
IEEE
14 years 6 days ago
2000
IEEE
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
DFT
1997
IEEE
14 years 20 hour ago
1997
IEEE
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...