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» Design space exploration for 3D architectures
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ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 10 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
SOUPS
2009
ACM
14 years 3 months ago
Social applications: exploring a more secure framework
Online social network sites, such as MySpace, Facebook and others have grown rapidly, with hundreds of millions of active users. A new feature on many sites is social applications...
Andrew Besmer, Heather Richter Lipford, Mohamed Sh...
MASCOTS
2007
13 years 10 months ago
Adaptive Sampling for Efficient MPSoC Architecture Simulation
—Modern micro-architecture simulators are many orders of magnitude slower than the hardware they simulate. The use of multiprocessor architectures for supporting future mobile an...
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar
CDES
2006
184views Hardware» more  CDES 2006»
13 years 10 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
DAC
2003
ACM
14 years 9 months ago
Microarchitecture evaluation with physical planning
Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical ...
Jason Cong, Ashok Jagannathan, Glenn Reinman, Mich...