Sciweavers

462 search results - page 88 / 93
» Design space exploration for 3D architectures
Sort
View
HPCA
2004
IEEE
14 years 7 months ago
Understanding Scheduling Replay Schemes
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
Ilhyun Kim, Mikko H. Lipasti
SIGCOMM
2009
ACM
14 years 1 months ago
Opportunistic forwarding in workplaces
So far, the search for Opportunistic Network (ON) applications has focused on urban/rural scenarios where the combined use of mobility and the store-carry-and-forward paradigm hel...
Sabrina Gaito, Elena Pagani, Gian Paolo Rossi
IEEEPACT
2007
IEEE
14 years 1 months ago
Automatic Correction of Loop Transformations
Loop nest optimization is a combinatorial problem. Due to the growing complexity of modern architectures, it involves two increasingly difficult tasks: (1) analyzing the profita...
Nicolas Vasilache, Albert Cohen, Louis-Noël P...
IEEEPACT
2005
IEEE
14 years 1 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
FPL
2007
Springer
97views Hardware» more  FPL 2007»
13 years 11 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee