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MICRO
2003
IEEE
95views Hardware» more  MICRO 2003»
15 years 11 months ago
Processor Acceleration Through Automated Instruction Set Customization
Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded appl...
Nathan Clark, Hongtao Zhong, Scott A. Mahlke
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
16 years 6 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
CEE
2007
110views more  CEE 2007»
15 years 5 months ago
HW/SW co-design for public-key cryptosystems on the 8051 micro-controller
It is a challenge to implement large word length public-key algorithms on embedded systems. Examples are smartcards, RF-ID tags and mobile terminals. This paper presents a HW/SW c...
Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid...
NSDI
2007
15 years 8 months ago
Beyond One-Third Faulty Replicas in Byzantine Fault Tolerant Systems
Byzantine fault tolerant systems behave correctly when no more than f out of 3f + 1 replicas fail. When there are more than f failures, traditional BFT protocols make no guarantee...
Jinyuan Li, David Mazières
172
Voted
RTCSA
2007
IEEE
16 years 3 days ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...