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DAC
1997
ACM
14 years 3 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak
JSA
2000
96views more  JSA 2000»
13 years 10 months ago
Design techniques for low-power systems
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power d...
Paul J. M. Havinga, Gerard J. M. Smit
VLSISP
2008
147views more  VLSISP 2008»
13 years 9 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
14 years 11 months ago
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
Yunsi Fei, Niraj K. Jha
DAC
2007
ACM
14 years 12 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy