— With the success of formal verification techniques like equivalence checking and model checking for hardware designs, there has been growing interest in applying such techniqu...
Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Mala...
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
To achieve scalability of query answering, the developers of Semantic Web applications are often forced to use incomplete OWL 2 reasoners, which fail to derive all answers for at ...
Bernardo Cuenca Grau, Boris Motik, Giorgos Stoilos...
Abstract—Plugin-based application design has become increasingly popular in recent years, and has contributed to the success of a range of very different applications including ...