11 search results - page 2 / 3 » Designing CMOS molecular memories while considering device p... |
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
CODES
2010
IEEE
13 years 5 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significa...
TVLSI
2010
13 years 2 months ago
2010
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
BROADNETS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we address three challenges that are present when building and analyzing wireless sensor networks (WSN) as part of ubiquitous computing environment: the need for an ...