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DFT
1997
IEEE
93views VLSI» more  DFT 1997»
14 years 1 months ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...
ICCAD
1997
IEEE
106views Hardware» more  ICCAD 1997»
14 years 1 months ago
BIST TPG for faults in system backplanes
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
Chen-Huan Chiang, Sandeep K. Gupta
SMA
1997
ACM
120views Solid Modeling» more  SMA 1997»
14 years 1 months ago
The Generic Geometric Complex (GGC): A Modeling Scheme for Families of Decomposed Pointsets
: Modeling of families of geometric objects is a major topic in modern geometric and solid modeling. Object families are central to many important solid modeling applications, incl...
Ari Rappoport
FPGA
1997
ACM
145views FPGA» more  FPGA 1997»
14 years 1 months ago
Generation of Synthetic Sequential Benchmark Circuits
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
CNSR
2010
IEEE
140views Communications» more  CNSR 2010»
14 years 22 days ago
Performance Evaluation of Using a Dynamic Shortest Path Algorithm in OLSRv2
—MANET routing protocols are designed to scale up to thousands of routers with frequent changes of the topology. In preference, MANET routing protocols should also support constr...
Ulrich Herberg