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DAC
2007
ACM
14 years 8 months ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
ISLPED
2004
ACM
157views Hardware» more  ISLPED 2004»
14 years 29 days ago
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...
Stefanos Kaxiras, Polychronis Xekalakis
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
13 years 5 months ago
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs
Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-...
Young-Joon Lee, Rohan Goel, Sung Kyu Lim
HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
14 years 4 months ago
Timing optimization by restructuring long combinatorial paths
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
Jürgen Werber, Dieter Rautenbach, Christian S...