63 search results - page 5 / 13 » Designing High Bandwidth On-Chip Caches |
CLUSTER
2008
IEEE
14 years 2 months ago
2008
IEEE
—Remote atomic memory operations are critical for achieving high-performance synchronization in tightly-coupled systems. Previous approaches to implementing atomic memory operati...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
MICRO
2003
IEEE
14 years 24 days ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...