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» Designing High Bandwidth On-Chip Caches
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GCC
2003
Springer
14 years 22 days ago
Improving Topology-Aware Routing Efficiency in Chord
Due to their minimum consideration to an actual network topology, the existing peer-to-peer (P2P) overlay networks will lead to high latency and low efficiency. In TaChord, we pres...
Dongfeng Chen, Shoubao Yang
ICDCS
2007
IEEE
14 years 1 months ago
STEP: Sequentiality and Thrashing Detection Based Prefetching to Improve Performance of Networked Storage Servers
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
Shuang Liang, Song Jiang, Xiaodong Zhang
MICRO
2002
IEEE
122views Hardware» more  MICRO 2002»
14 years 13 days ago
Microarchitectural denial of service: insuring microarchitectural fairness
Simultaneous multithreading seeks to improve the aggregate computation bandwidth of a processor core by sharing resources such as functional units, caches, TLB and so on. To date,...
Dirk Grunwald, Soraya Ghiasi
WWW
2011
ACM
13 years 2 months ago
Track globally, deliver locally: improving content delivery networks by tracking geographic social cascades
Providers such as YouTube offer easy access to multimedia content to millions, generating high bandwidth and storage demand on the Content Delivery Networks they rely upon. More ...
Salvatore Scellato, Cecilia Mascolo, Mirco Musoles...
HPCA
2005
IEEE
14 years 1 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...