Sciweavers

96 search results - page 6 / 20
» Designing a Coprocessor for Recurrent Computations
Sort
View
HPCA
1997
IEEE
13 years 11 months ago
ATM and Fast Ethernet Network Interfaces for User-Level Communication
Fast Ethernet and ATM are two attractive network technologies for interconnecting workstation clusters for parallel and distributed computing. This paper compares network interfac...
Matt Welsh, Anindya Basu, Thorsten von Eicken
CHES
2009
Springer
162views Cryptology» more  CHES 2009»
14 years 8 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...
ARITH
2007
IEEE
14 years 1 months ago
Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit ...
Neil Burgess, Chris N. Hinds
ANCS
2006
ACM
14 years 1 months ago
Design of a web switch in a reconfigurable platform
The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In...
Christoforos Kachris, Stamatis Vassiliadis
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
14 years 1 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll